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DDRII Unbuffered DIMM

  

DDR2 533/667/800




Feature
* JEDEC standard 1.7V~ 1.9V Power Supply.
* VDDQ = 1.7V~1.9V
* 267MHz fCK for 533Mb/sec/pin, 333MHz fCKfor 667Mb/sec/pin,400MHz fCK for 800Mb/sec/pin
* 4 Banks
* Posted /CAS
* Programmable /CAS Latency: 4,5.
* Programmable Additive Latency: 0, 1 , 2 , 3 and 4.
* Write Latency(WL) = Read Latency(RL) -1.
* Burst Length : 4 , 8(Interleave/nibble sequential).
* Programmable Sequential / Interleave Burst Mode.
* Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature).
* Off-Chip Driver(OCD) Impedance Adjustment.
* On Die Termination with selectable values(50/75/150 ohms or disable).
* PASR(Partial Array Self Refresh).
* Average Refresh Period 7.8us at lower than a TCASE 85°C, 3.9us at 85°C < TCASE 95°C.
- support High Temperature Self-Refresh rate enable feature.
* All of Lead-free products are compliant for RoHS.

 
Density (Mbytes) Organization Speed Component Composition
256 32M * 64 PC4200 / 5300 32M * 8 * 8ea
256 32M * 64 PC4200 / 5300 32M * 16 * 4ea
512 64M * 64 PC4200 / 5300 32M * 8 * 16ea
512 64M * 64 PC4200 / 5300 32M *16 * 8ea
512 64M * 64 PC4200 / 5300 64M * 8 * 8ea
1024 128M * 64 PC4200 / 5300 64M * 8 * 16ea

 

DDRII Unbuffered SODIMM

  

DDR2 533/667/800

 
* JEDEC standard 1.7V~ 1.9V Power Supply.
* VDDQ = 1.7V~ 1.9V
* 267MHz fCK for 533Mb/sec/pin, 333MHz fCKfor 667Mb/sec/pin,400MHz fCK for 800Mb/sec/pin
* 4 Banks
* Posted /CAS
* Programmable /CAS Latency: 4,5.
* Programmable Additive Latency: 0, 1 , 2 , 3 and 4.
* Write Latency(WL) = Read Latency(RL) - 1.
* Burst Length : 4, 8(Interleave/nibble sequential).
* Programmable Sequential / Interleave Burst Mode.
* Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature).
* Off-Chip Driver(OCD) Impedance Adjustment.
* On Die Termination.
* Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE 95°C.
- support High Temperature Self-Refresh rate enable feature.
* All of Lead-free products are compliant for RoHS.

 
Density (Mbytes) Organization Speed Component Composition
256 32M * 64 PC4200 / 5300 32M * 8 * 8ea
256 32M * 64 PC4200 / 5300 32M * 16 * 4ea
512 64M * 64 PC4200 / 5300 32M * 8 * 16ea
512 64M * 64 PC4200 / 5300 32M *16 * 8ea
512 64M * 64 PC4200 / 5300 64M * 8 * 8ea
1024 128M * 64 PC4200 / 5300 64M * 8 * 16ea

 

DDRII Unbuffered DIMM

  

DDR3 800/1066/1333/1600



 
* VDDQ = 1.5V (+/-) 0.075V
* 8 independent internal bank
* Programmable /CAS Latency : (4), 5, 6, 7, 8, 9, 10, (11 for high density only)
* Programmable /CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333), 8 (DDR3-1600)
* 8-bit pre-fetch
* Bi-directional Differential Data-Strobe
* Internal(self) calibration
* On Die Termination using ODT pin
* Average Refresh Period 7.8us at lower than TCASE 85¢XC, 3.9us at 85¢XC < TCASE ? 95¢XC
* All of Lead-free products are compliant for RoHS
 
Density (Mbytes) Organization Speed Component Composition
1GB 128M * 64 PC3-8500 / 10600 64M * 8 * 16ea
1GB 128M * 64 PC3-8500 / 10600 128M * 8 * 8ea
2GB 256M * 64 PC3-8500 / 10600 128M * 8 * 16ea
2GB 256M * 64 PC3-8500 / 10600 256M * 8 * 8ea
4G 512M * 64 PC3-8500 / 10600 256M *16 * 8ea

 
 
 
     
 

EXCEPTIONAL QUALITY . PROVEN INDUSTRY LEADER . 100% COMPATIBILITY GUARANTEE

 
 
TOPRAM Memory Modules undergo a thorough rigorous quality control and monitored testing procedures to ensure the highest quality and guaranteed compatibility. TOPRAM is setup to assure customers the world-class quality products.